The following descriptions and examples are given as background only.
Integrated circuits are susceptible to damage from application of excessive electrical charge, such as those generated during electrostatic discharge (ESD) events. For example, integrated circuits (ICs) may be exposed to electrostatic charges during manufacturing of the integrated circuit (wafer level), handling of the integrated circuit after packaging and/or handling of a printed circuit board after assembly. In some cases, an integrated circuit may be exposed to the charges that arise from the use of plasma etching techniques or other fabrication processes that produce charged particles. In other cases, a packaged integrated circuit may be exposed to electrostatic charges when a person inadvertently touches the exposed pins on the circuit package, or when the package becomes electro-statically charged due to movement of the package across an electrically-conductive surface.
The electrical pulse transferred to an integrated circuit (IC) during an ESD event can inflict significant damage to sensitive components of the integrated circuit. For example, transistors and other electrical devices on an integrated circuit may be damaged when an excessive amount of charge is transferred between one or more pins of the integrated circuit and another conducting object over a short time period, usually between tens and hundreds of nanoseconds. The transferred charge (referred to as electrostatic discharge) can develop voltages that are large enough to break down insulating films on the circuit (such as gate oxides), or dissipate sufficient energy to cause electro-thermal failures in the circuit (such as contact spiking, silicon melting and metal interconnect melting).
Accordingly, others have attempted develop methods to protect integrated circuits, with particular attention to the problem of protecting field effect transistor (FET) devices and other sensitive circuitry from ESD events. In some cases, ESD protection devices are connected between the input/output (I/O) pads and internal circuitry of an IC to redirect the energy generated during an ESD event away from the sensitive circuitry. Protection devices may also be connected to power supply pads or between power supply buses to prevent damage during ESD events. So far these devices have been unable to fully solve existing and constantly evolving ESD problems. Existing devices can be overly sensitive to initial normal power up conditions, mistakenly redirecting normal power up voltages to ground and generating unnecessary and undesirable voltage spiking in the IC. Such “false positives” are highly undesirable and interfere with the normal function of the internal circuitry. In attempting to correct this oversensitivity to “false positives” and other normal power conditions, others have attempted to build protection circuits that are sensitive enough to distinguish normal power up from ESD events. Known circuits of this type frequently do not stay active long enough to sufficiently discharge the ESD event. Thus, the residual undischarged ESD energy is quite capable of overloading and damaging the protected circuitry.
In one prior art approach, an ESD protection device uses a “snapback devices,” or devices which rely on parasitic bipolar devices, including bipolar junction transistors (BJTs) and thyristors which are inherent in most semiconductor integrated circuits. These bipolar devices can include those devices normally considered parasitic devices in technologies that use field effect transistors (FET) such as complementary metal-oxide-semiconductor (CMOS) based integrated circuits. During an ESD event, the bipolar device can enter a conductive state to safely dissipate the ESD discharge. Although such snapback devices are often used within ESD protection devices, they are not without disadvantages. For example, it is hard to predict/control the behavior of actual snapback devices fabricated in silicon, since the behavior of their parasitic BJTs cannot be accurately simulated (due to the fact that snapback devices operate in a region (the snapback region) which is largely unmodeled) and their parameters can be difficult to control in an actual implementation. This lack of predictability can lead to inferior ESD protection performance or over-designed networks or both. Consequently, such ESD protection schemes can consume relatively large amounts of silicon area and can affect the stand-by current budgets of the chips they are used in.
In other attempts to solve these problems, active shunt networks (otherwise referred to as “actively switched networks” or “rail-based networks”) are used to implement ESD protection. Within such networks, the ESD voltage is conducted through an actively switched network. Such circuits are intended to differentiate between normal operation of the integrated circuit and an ESD event. Advantageously, such active networks can be simulated using conventional circuit simulators, resulting in more predictable protection from ESD discharges, which can take comparatively less area for the same ESD performance. However, active network circuits suffer from some serious limitations and can fail provide adequate ESD protection in all cases. As with snapback devices, the behavior of active network circuitry is also hard to control over process variations. Process variations within many of the circuit components may influence the operation of the trigger circuit by shifting the respective ESD activation conditions to a substantially higher or lower level. In some cases, the active network circuits may fail to protect the internal circuitry from a true ESD event due to process variations that affect the ESD protection circuitry operating parameters. Such failure may allow a potentially damaging electrostatic charge to be supplied to the internal circuitry of an integrated circuit. Typically, the sensitivity of these networks can be adjusted using experimental data. For example, the ESD event sensitivity of a particular active network circuit design may be tested after the respective integrated circuit had been fabricated. If the active network circuit fails to completely discharge an ESD event, the process parameters of the ESD protection circuit are typically altered in order to obtain the desired ESD performance. Once the appropriate changes are made, the integrated circuit may be taped-out again and the ESD protection may be re-verified in the lab once the circuit is fabricated. The process may then continue by trial-and-error until the active network circuit is provided with sufficient sensitivity to detect ESD events (i.e., the ESD protection provided to the integrated circuit meets certain ESD requirements). Unfortunately, such a process is time consuming and costly. In addition, the ESD circuits resulting from such a process cannot be reused for other chips (e.g., with different sizes and/or ESD requirements). Accordingly, customized circuits must be designed and tested for each new circuit.
Other known solutions include simple circuits that have a single RC time constant that is varied depending on the manufacturer and design requirements. In the prior art, ESD circuitry having short RC time constants are employed. Although such circuits are sensitive to ESD events they suffer from an inability to sufficiently discharge ESD events and so do not provide the desired level of ESD protection. ESD protection circuits employing longer RC time constants feature improved discharge capability, but suffer from the inability to effectively distinguish ordinary operational and systemic noise from actual ESD events thereby seriously limiting their usefulness.
Additionally, programmable ESD protection circuits have also been invented. However, these circuits are large, complicated, and require programming time that can substantially increase the cost.
Accordingly, there is a need for improved ESD protection circuitry.